Project

General

Profile

Bug #8855

VerilogIeeeTestCase.runTest_10_03_00_5: java.lang.IllegalArgumentException

Added by Sergey Smolov about 2 years ago. Updated almost 2 years ago.

Status:
Closed
Priority:
Normal
Target version:
Start date:
05/07/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

History

#1

Updated by Sergey Smolov about 2 years ago

  • Detected in build changed from svn to master
  • Target version set to 0.1
  • Assignee set to Alexander Kamkin
#2

Updated by Sergey Smolov about 2 years ago

  • Subject changed from VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException to VerilogIeeeTestCase.runTest_10_03_00_5: java.lang.IllegalArgumentException

The stack trace:

java.lang.IllegalArgumentException
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
    at ru.ispras.verilog.parser.core.AbstractNode.add(AbstractNode.java:343)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5166)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4109)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5163)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4109)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3194)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:938)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:666)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:508)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:458)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:242)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:247)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:262)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:266)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:162)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_03_00_5(VerilogIeeeTestCase.java:899)

The target Verilog module:

// IEEE Std 1364-2005
//   10. Tasks and functions
//     10.3 Disabling of named blocks and tasks
//       This example shows the disable statement being used to disable concurrently a sequence of
//       timing controls and the task action when the reset event occurs. The example shows a
//       fork-join block within which are a named sequential block (event_expr) and a disable
//       statement that waits for occurrence of the event reset. The sequential block and the wait
//       for reset execute in parallel. The event_expr block waits for one occurrence of event ev1
//       and three occurrences of event trig. When these four events have happened, plus a delay
//       of d time units, the task action executes. When the event reset occurs, regardless
//       of events within the sequential block, the fork-join block terminates—including the task
//       action.

module test;
  parameter d = 1;
  input clk, ev1, trig;
  reg areg, breg;

  task action;
    input areg, breg;
    reg temp;
    begin
      temp = areg + breg;
    end
  endtask

  initial begin
    fork
      begin : posedge(clk)
        @ev1;
        repeat (3) @trig;
        #d action (areg, breg);
      end
      @reset disable posedge(clk);
  join
  end
endmodule

#3

Updated by Alexander Kamkin almost 2 years ago

  • Status changed from New to Resolved

Incorrect test: begin: posedge(clk) -> begin: event_expr.

#4

Updated by Sergey Smolov almost 2 years ago

  • Status changed from Resolved to Verified
#5

Updated by Sergey Smolov almost 2 years ago

  • Status changed from Verified to Closed

Also available in: Atom PDF