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Bug #8854

VerilogIeeeTestCase.runTest_05_02_02_2: java.lang.NullPointerException

Added by Sergey Smolov almost 2 years ago. Updated over 1 year ago.

Status:
Closed
Priority:
Normal
Target version:
Start date:
05/07/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

The stack trace:

java.lang.NullPointerException
    at ru.ispras.fortress.expression.TypeRules$15.getResultType(TypeRules.java:196)
    at ru.ispras.fortress.expression.StandardOperation.getResultType(StandardOperation.java:535)
    at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:195)
    at ru.ispras.fortress.expression.Node.isType(Node.java:177)
    at ru.ispras.fortress.expression.ExprUtils.isType(ExprUtils.java:84)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer$3.apply(VerilogExprTransformer.java:214)
    at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
    at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:226)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
    at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
    at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:62)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:159)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:170)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:189)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.onAssignStatementBegin(VerilogTransformer.java:78)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
    at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
    at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:85)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.run(VerilogTransformer.java:53)
    at ru.ispras.verilog.parser.elaborator.VerilogVariableSubstitutor.transform(VerilogVariableSubstitutor.java:44)
    at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateProcess(VerilogInstantiator.java:88)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:185)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:173)
    at ru.ispras.verilog.parser.sample.VerilogDesignPrinter.start(VerilogDesignPrinter.java:36)
    at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_05_02_02_2(VerilogIeeeTestCase.java:313)

The target Verilog module:

// IEEE Std 1364-2005
//   5. Expressions
//    5.2 Operands
//      5.2.2 Array and memory addressing
//        The next example declares an array of 256-by-256 eight-bit elements and an array
//        256-by-256-by-8 one-bit elements

module test;
  reg [7:0] twod_array[0:255][0:255];
  wire threed_array[0:255][0:255][0:7];
  reg [7:0] twod_array_result;
  reg threed_array_result;
  integer addr_expr;
  reg [3:0] lower_result;
  reg sixth_bit;
  integer sel;
  reg sel_result;
  reg [3:0] illegal_result;

  initial begin
    twod_array_result = twod_array[addr_expr][addr_expr];
    threed_array_result = threed_array[addr_expr][addr_expr][addr_expr];

    lower_result = twod_array[14][1][3:0]; // access lower 4 bits of word
    sixth_bit = twod_array[1][3][6]; // access bit 6 of word
    sel_result = twod_array[1][3][sel]; // use variable bit-select
    `ifdef NEGATIVE_TEST
    illegal_result = threed_array[14][1][3:0]; // Illegal
    `endif
  end

endmodule

History

#1

Updated by Alexander Kamkin over 1 year ago

  • Status changed from New to Resolved
#2

Updated by Sergey Smolov over 1 year ago

  • Status changed from Resolved to Verified
#3

Updated by Sergey Smolov over 1 year ago

  • Status changed from Verified to Closed

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