Bug #8853: VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException - Verilog Translator - Open-Source Projects

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Bug #8853

closed

VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException

Added by Sergey Smolov over 6 years ago. Updated over 6 years ago.

Status:

Closed

Priority:

Normal

Assignee:

Alexander Kamkin

Target version:

0.1

Start date:

05/07/2018

Due date:

% Done:

Estimated time:

Detected in build:

master

Platform:

Published in build:

Description

The stack trace:

java.lang.IllegalArgumentException
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
    at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer$3.apply(VerilogExprTransformer.java:210)
    at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
    at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:226)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
    at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
    at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:62)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:151)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:184)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.onAssignStatementBegin(VerilogTransformer.java:78)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
    at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
    at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:85)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.run(VerilogTransformer.java:53)
    at ru.ispras.verilog.parser.elaborator.VerilogVariableSubstitutor.transform(VerilogVariableSubstitutor.java:44)
    at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateProcess(VerilogInstantiator.java:88)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:185)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:173)
    at ru.ispras.verilog.parser.sample.VerilogDesignPrinter.start(VerilogDesignPrinter.java:36)
    at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_05_02_01_2(VerilogIeeeTestCase.java:293)

The target Verilog module:

// IEEE Std 1364-2005
//   5. Expressions
//    5.2 Operands
//      5.2.1 Vector bit-select and part-select addressing
module test;
  reg [31: 0] big_vect;
  reg [0 :31] little_vect;
  reg [63: 0] dword;
  integer sel;

  initial begin
    big_vect[ 0 +: 8]    = 8'b1010_1010; // == big_vect[ 7 : 0]
    big_vect[15 -: 8]    = 8'b1010_1010; // == big_vect[15 : 8]
    little_vect[ 0 +: 8] = 8'b1010_1010; // == little_vect[0 : 7]
    little_vect[15 -: 8] = 8'b1010_1010; // == little_vect[8 :15]
    dword[8*sel +: 8]    = 8'b1010_1010; // variable part-select with fixed width
  end
endmodule

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Updated by Sergey Smolov over 6 years ago

Same error comes for:

VerilogIeeeTestCase.runTest_05_02_01_4 test case
The target Verilog module:

// IEEE Std 1364-2005
//   5. Expressions
//    5.2 Operands
//      5.2.1 Vector bit-select and part-select addressing
//        Example 2 - The next example and the bullet items that follow it illustrate the
//        principles of bit addressing. The code declares an 8-bit reg called vect and
//        initializes it to a value of 4. The list describes how the separate bits of that vector
//        can be addressed.
module test;
  reg [7:0] vect;

  reg [3:0] addr;
  reg [7:0] result;

  initial begin
    vect = 4; // fills vect with the pattern 00000100
              // msb is bit 7, lsb is bit 0

    // If the value of addr is 2, then vect[addr] returns 1.
    addr = 2;
    result[0] = vect[addr];

    // If the value of addr is out of bounds, then vect[addr] returns x.
    addr = 123;
    result[0] = vect[addr];

    // If addr is 0, 1, or 3 through 7, vect[addr] returns 0.
    addr = 0;
    result[0] = vect[addr];

    // vect[3:0] returns the bits 0100.
    result[3:0] = vect[3:0];

    // vect[5:1] returns the bits 00010.
    result[5:1] = vect[5:1];

    // vect[expression that returns x] returns x.
    addr = x;
    result[0] = vect[addr];

    // vect[expression that returns z] returns x.
    addr = z;
    result[0] = vect[addr];

    // If any bit of addr is x or z, then the value of addr is x.
    addr = 4'b0x1z;
    result[0] = vect[addr];
  end
endmodule

VerilogIeeeTestCase.runTest_09_07_05_5 test case
The target Verilog module:

// IEEE Std 1364-2005
//   9. Behavioral modeling
//     9.7 Procedural timing controls
//       9.7.4 Event or operator
//         Nets and variables that appear on the right-hand side of assignments, in function and
//         task calls, in case and conditional expressions, as an index variable on the left-hand
//         side of assignments, or as variables in case item expressions shall all be included by
//         these rules.

module test;

  input a, en;
  reg [7 : 0] y;

  always @* begin // same as @(a or en)
    y = 8'hff;
    y[a] = !en;
  end
endmodule

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