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Bug #8851

VerilogIeeeTestCase.runTest_05_01_14_3: java.lang.IllegalArgumentException: 0 must be > 0

Added by Sergey Smolov over 1 year ago. Updated over 1 year ago.

Status:
Closed
Priority:
Normal
Target version:
Start date:
05/07/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

The stack trace:

java.lang.IllegalArgumentException: 0 must be > 0
    at ru.ispras.fortress.util.InvariantChecks.checkGreaterThanZero(InvariantChecks.java:159)
    at ru.ispras.fortress.data.DataType.bitVector(DataType.java:71)
    at ru.ispras.fortress.expression.TypeRules$12.getResultType(TypeRules.java:176)
    at ru.ispras.fortress.expression.StandardOperation.getResultType(StandardOperation.java:535)
    at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:195)
    at ru.ispras.fortress.expression.Node.isType(Node.java:177)
    at ru.ispras.fortress.expression.ExprUtils.isType(ExprUtils.java:84)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer$3.apply(VerilogExprTransformer.java:214)
    at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
    at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:226)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
    at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
    at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:62)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:159)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:170)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:189)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.onAssignStatementBegin(VerilogTransformer.java:78)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
    at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
    at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:79)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.run(VerilogTransformer.java:53)
    at ru.ispras.verilog.parser.elaborator.VerilogVariableSubstitutor.transform(VerilogVariableSubstitutor.java:44)
    at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateProcess(VerilogInstantiator.java:88)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:185)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:173)
    at ru.ispras.verilog.parser.sample.VerilogDesignPrinter.start(VerilogDesignPrinter.java:36)
    at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_05_01_14_3(VerilogIeeeTestCase.java:278)

The target Verilog module:

// IEEE Std 1364-2005
//   5. Expressions
//    5.1 Operators
//      5.1.14 Concatenations
//        Example 3
module test;
  parameter P = 32;

  reg [31:0] a;
  wire [31:0] b;
  wire [31:0] c;

  // The following is legal for all P from 1 to 32
  assign b[31:0] = { {32-P{1'b1}}, a[P-1:0] } ;

`ifdef NEGATIVE_TEST
  // The following is illegal for P=32 because the zero
  // replication appears alone within a concatenation
  assign c[31:0] = { {{32-P{1'b1}}}, a[P-1:0] }

  // The following is illegal for P=32
  initial
    $displayb({32-P{1'b1}}, a[P-1:0]);
`endif
endmodule

History

#1

Updated by Alexander Kamkin over 1 year ago

  • Status changed from New to Resolved

VerilogConcatTransformer, which removes empty BVREPEAT from BVCONCAT, has been implemented.

#2

Updated by Sergey Smolov over 1 year ago

  • Status changed from Resolved to Verified
#3

Updated by Sergey Smolov over 1 year ago

  • Status changed from Verified to Closed

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