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Bug #8849

closed

VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException

Added by Sergey Smolov almost 6 years ago. Updated over 3 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
05/07/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
0.1.3-beta-201002

Description

The tool stack trace:

java.lang.IllegalArgumentException
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
    at ru.ispras.verilog.parser.model.basis.VerilogLiteral.getBitVector(VerilogLiteral.java:274)
    at ru.ispras.verilog.parser.calculator.VerilogOperations$9.calculate(VerilogOperations.java:202)
    at ru.ispras.fortress.calculator.OperationGroup.calculate(OperationGroup.java:145)
    at ru.ispras.fortress.transformer.Reducer$OperationRule.apply(Reducer.java:148)
    at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
    at ru.ispras.fortress.transformer.NodeTransformer.updateNode(NodeTransformer.java:176)
    at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:224)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
    at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
    at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:184)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer.evaluate(VerilogExprTransformer.java:93)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.evaluate(VerilogElaborator.java:698)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.defineParameter(VerilogElaborator.java:626)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createBindings(VerilogElaborator.java:515)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createBindings(VerilogElaborator.java:481)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:275)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:181)
    at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:56)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:163)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_04_10_01_1(VerilogIeeeTestCase.java:183)

The target Verilog module:

// IEEE Std 1364-2005
//   4. Data types
//    4.10 Parameters
//      4.10.1 Module parameters
module test;
  parameter msb = 7;                 // defines msb as a constant value 7
  parameter e = 25, f = 9;           // defines two constant numbers
  parameter r = 5.7;                 // declares r as a real parameter
  parameter byte_size = 8,
            byte_mask = byte_size - 1;
  parameter average_delay = (r + f) / 2;
  parameter signed [3:0] mux_selector = 0;
  parameter real r1 = 3.5e17;
  parameter p1 = 13'h7e;
  parameter [31:0] dec_const = 1'b1; // value converted to 32 bits
  parameter newconst = 3'h4;         // implied range of [2:0]
  parameter newconst2 = 4;            // implied range of at least [31:0]
endmodule

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