Verilog Translator

This error appears when running ru.ispras.verilog.parser.sample.vcegar.VcegarIpbdpHierVerilogPrinterTestCase in the Retrascope MC Benchmark project.

The corresponding Verilog file:

retrascope-mc-benchmark/src/main/verilog/vcegar-benchmarks/ipbdp/ipbdp_hier.v

The error log:

Bit vector sizes do not match: 4 != 32.
java.lang.IllegalArgumentException: Bit vector sizes do not match: 4 != 32.
    at ru.ispras.fortress.data.types.bitvector.BitVectorMath.checkEqualSize(BitVectorMath.java:938)
    at ru.ispras.fortress.data.types.bitvector.BitVectorMath.transform(BitVectorMath.java:914)
    at ru.ispras.fortress.data.types.bitvector.BitVectorMath.add(BitVectorMath.java:682)
    at ru.ispras.fortress.data.types.bitvector.BitVectorMath.sub(BitVectorMath.java:695)
    at ru.ispras.verilog.parser.calculator.VerilogOperations$10.calculate(VerilogOperations.java:224)
    at ru.ispras.fortress.calculator.OperationGroup.calculate(OperationGroup.java:145)
    at ru.ispras.fortress.transformer.Reducer$OperationRule.apply(Reducer.java:148)
    at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
    at ru.ispras.fortress.transformer.NodeTransformer.updateNode(NodeTransformer.java:176)
    at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:224)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
    at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
    at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:184)
    at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:249)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer.reduce(VerilogExprTransformer.java:77)
    at ru.ispras.verilog.parser.model.basis.VerilogExpression.reduce(VerilogExpression.java:337)
    at ru.ispras.verilog.parser.model.basis.VerilogExpression.reduce(VerilogExpression.java:349)
    at ru.ispras.verilog.parser.processor.VerilogProcessorContextUtils.reduceExpression(VerilogProcessorContextUtils.java:66)
    at ru.ispras.verilog.parser.processor.VerilogStaticChecker.reduce(VerilogStaticChecker.java:579)
    at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:349)
    at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:366)
    at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:388)
    at ru.ispras.verilog.parser.processor.VerilogStaticChecker.onAssignBegin(VerilogStaticChecker.java:106)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$2.onBegin(VerilogNodeVisitor.java:253)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
    at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
    at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:85)
    at ru.ispras.verilog.parser.VerilogSyntaxBackend.start(VerilogSyntaxBackend.java:80)
    at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:56)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:163)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:51)
    at ru.ispras.verilog.parser.sample.VerilogPrinterTest.runTest(VerilogPrinterTest.java:48)