Verilog Translator

This error appears when running ru.ispras.verilog.parser.sample.vcegar.VcegarMpegVerilogPrinterTestCase in the Retrascope MC Benchmark project.
The corresponding Verilog file:

retrascope-mc-benchmark/src/main/verilog/vcegar-benchmarks/mpeg/mpeg_1.v

The error:

java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95)
at ru.ispras.fortress.expression.NodeOperation.<init>(NodeOperation.java:117)
at ru.ispras.fortress.expression.NodeOperation.<init>(NodeOperation.java:70)
at ru.ispras.fortress.expression.NodeOperation.<init>(NodeOperation.java:52)
at ru.ispras.verilog.parser.processor.VerilogExprTransformer$4.apply(VerilogExprTransformer.java:254)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:226)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:61)
at ru.ispras.verilog.parser.processor.VerilogProcessorContextUtils.reduceExpression(VerilogProcessorContextUtils.java:69)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.reduce(VerilogStaticChecker.java:579)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:349)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.onIfStatementBegin(VerilogStaticChecker.java:167)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$20.onBegin(VerilogNodeVisitor.java:469)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:85)
at ru.ispras.verilog.parser.VerilogSyntaxBackend.start(VerilogSyntaxBackend.java:80)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:56)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:163)
...