Verilog Translator

The current grammar conforms the IEEE 1364-2005 Std.

if_generate
    : KW_IF LPAREN cond=expression RPAREN
        then_body=generate_block_or_null
        ((KW_ELSE)=> KW_ELSE else_body=generate_block_or_null)?
;

generate_block
    : module_or_generate_item
    | KW_BEGIN
        (module_or_generate_item)*
      KW_END
;

generate_block_or_null
    : generate_block
    | SEMI!
;

However, there industrial designs (e.g., Altera's ones) that use syntax.

if (...) begin
 ...
else if (...) begin
...
end