Verilog Translator

module test;
  specify
    specparam tRise_clk_q = 150, tFall_clk_q = 200;
    specparam tRise_control = 40, tFall_control = 50;
  endspecify
endmodule

veritrans\src\test\verilog\ieee-tests\test_04_10_3_1.v line 23:50 mismatched input ';' expecting KW_ENDSPECIFY
veritrans\src\test\verilog\ieee-tests\test_04_10_3_1.v line 25:2 extraneous input 'endspecify' expecting KW_ENDMODULE
ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 21:0 mismatched tree node: <mismatched token: [@12,807:807=';',<201>,23:50], resync=specifyspecparamtRise_clk_q=150,tFall_clk_q=200;> expecting <UP>