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Bug #8802

ClassCastException in vcegar-benchmarks/miim

Added by Mikhail Lebedev almost 2 years ago. Updated almost 2 years ago.

Status:
Closed
Priority:
Normal
Target version:
Start date:
04/04/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Platform:
Published in build:

Description

This error appears when running ru.ispras.verilog.parser.sample.VcegarMiimVerilogPrinterTestCase in the Retrascope MC Benchmark project.
The corresponding Verilog file:

retrascope-mc-benchmark/src/main/verilog/vcegar-benchmarks/miim/vMiim.v

Tool log:

Module name: main
Including file 'C:\Users\lebedev.INTRA\workspace\retrascope-mc-benchmark\src\main\verilog\vcegar-benchmarks\miim\vMiim.v' ...
java.lang.ClassCastException: ru.ispras.verilog.parser.model.VerilogPortConnection cannot be cast to ru.ispras.verilog.parser.model.VerilogDeclaration
at ru.ispras.verilog.parser.model.util.ModelUtils.getNode(ModelUtils.java:157)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_primary(VerilogTreeBuilder.java:6325)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6159)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6014)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_port_connection(VerilogTreeBuilder.java:3376)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_instantiation(VerilogTreeBuilder.java:3301)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:947)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:665)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:507)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:457)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:240)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:245)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:256)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:260)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:162)

Veritrans options:

--module-name main

History

#1

Updated by Mikhail Lebedev almost 2 years ago

Also detected in
retrascope-mc-benchmark/src/main/verilog/vcegar-benchmarks/pj_icu/icctl1.v

#2

Updated by Alexander Kamkin almost 2 years ago

  • Status changed from New to Resolved

There are a declaration and a port connection with the same name. Searching for the declaration returns the port connection. It causes the cast exception.

#3

Updated by Mikhail Lebedev almost 2 years ago

  • % Done changed from 0 to 100
  • Status changed from Resolved to Verified
#4

Updated by Alexander Kamkin almost 2 years ago

  • Status changed from Verified to Closed

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