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Bug #8779

mips16/data_mem.v: wrong type for define-containing declaration of 'ram_addr' wire

Added by Sergey Smolov almost 2 years ago. Updated almost 2 years ago.

Status:
Closed
Priority:
Normal
Target version:
Start date:
03/23/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

The right-hand side of following statement:

wire [`DATA_MEM_ADDR_WIDTH-1 : 0] ram_addr = mem_access_addr[`DATA_MEM_ADDR_WIDTH-1 : 0];

is represented by Verilog Translator as follows (SMT_LIB format):
(BVEXTRACT 2 0 (BVEXTRACT 7 0 mem_access_addr))

The left-hand side has no ranges - it contains "ram_addr" variable only.

History

#1

Updated by Sergey Smolov almost 2 years ago

  • Subject changed from mips16/data_mem.v: wrong right-hand side expression in assignment to mips16/data_mem.v: wrong type for define-containing declaration of 'ram_addr' wire
#2

Updated by Alexander Kamkin almost 2 years ago

  • Status changed from New to Resolved
#3

Updated by Alexander Kamkin almost 2 years ago

  • Status changed from Resolved to Closed

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