mips16/data_mem.v: wrong type for define-containing declaration of 'ram_addr' wire
Detected in build:
Published in build:
The right-hand side of following statement:
wire [`DATA_MEM_ADDR_WIDTH-1 : 0] ram_addr = mem_access_addr[`DATA_MEM_ADDR_WIDTH-1 : 0];
is represented by Verilog Translator as follows (SMT_LIB format):
(BVEXTRACT 2 0 (BVEXTRACT 7 0 mem_access_addr))
The left-hand side has no ranges - it contains "ram_addr" variable only.