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Bug #8739

closed

VerilogStaticChecker causes an exception when handling variables with parameter-defined length

Added by Alexander Kamkin almost 7 years ago. Updated over 6 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
02/26/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Platform:
Published in build:

Description

The reason is clear. Parameters (except, probably, localparam) are considered as variables until the design is elaborated (they can be redefined in instances). VerilogStaticChecker works at the AST level.

A possible workaround is to use default values in VerilogStaticChecker and to use final values in VerilogElaborator.

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 #1

Updated by Alexander Kamkin over 6 years ago

  • Status changed from New to Resolved
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 #2

Updated by Alexander Kamkin over 6 years ago

  • Status changed from Resolved to Closed
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