Project

General

Profile

Actions
Copy link

Task #7723

closed

Support for module instances in Verilog descriptions

Added by Sergey Smolov over 7 years ago. Updated almost 6 years ago.

Status:
Rejected
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Engine (Parser)
Target version:
1.0
Start date:
11/14/2016
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:
Actions
Copy link
 #1

Updated by Sergey Smolov over 6 years ago

  • Target version changed from 0.2 to 1.0
Actions
Copy link
 #2

Updated by Sergey Smolov about 6 years ago

  • Status changed from New to Resolved
  • Assignee changed from Mikhail Chupilko to Sergey Smolov
  • % Done changed from 0 to 100
  • Detected in build changed from svn to master

The task has been moved to Verilog Translator project.
It is supposed, that Verilog design comes to Retrascope as completely instantiated model.

Actions
Copy link
 #3

Updated by Sergey Smolov almost 6 years ago

  • Status changed from Resolved to Rejected
Actions
Copy link

Also available in: Atom PDF