Task #7723: Support for module instances in Verilog descriptions - Retrascope - Open-Source Projects

Task #7723

Support for module instances in Verilog descriptions

Added by Sergey Smolov almost 3 years ago. Updated about 1 year ago.

Status:

Rejected

Priority:

Normal

Assignee:

Category:

Engine (Parser)

Target version:

Start date:

11/14/2016

Due date:

% Done:

100%

Estimated time:

Detected in build:

master

Published in build:

History

#1

Updated by Sergey Smolov almost 2 years ago

Target version changed from 0.2 to 1.0

#2

Updated by Sergey Smolov over 1 year ago

Detected in build changed from svn to master
% Done changed from 0 to 100
Assignee changed from Mikhail Chupilko to Sergey Smolov
Status changed from New to Resolved

The task has been moved to Verilog Translator project.
It is supposed, that Verilog design comes to Retrascope as completely instantiated model.

#3

Updated by Sergey Smolov about 1 year ago

Status changed from Resolved to Rejected

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