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Task #7723

closed

Support for module instances in Verilog descriptions

Added by Sergey Smolov about 7 years ago. Updated over 5 years ago.

Status:
Rejected
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Engine (Parser)
Target version:
1.0
Start date:
11/14/2016
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:
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 #1

Updated by Sergey Smolov about 6 years ago

  • Target version changed from 0.2 to 1.0
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 #2

Updated by Sergey Smolov over 5 years ago

  • Status changed from New to Resolved
  • Assignee changed from Mikhail Chupilko to Sergey Smolov
  • % Done changed from 0 to 100
  • Detected in build changed from svn to master

The task has been moved to Verilog Translator project.
It is supposed, that Verilog design comes to Retrascope as completely instantiated model.

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 #3

Updated by Sergey Smolov over 5 years ago

  • Status changed from Resolved to Rejected
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