Task #7723
Support for module instances in Verilog descriptions
Start date:
11/14/2016
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Published in build:
History
Updated by
Updated by Sergey Smolov almost 3 years ago
- Detected in build changed from svn to master
- % Done changed from 0 to 100
- Assignee changed from Mikhail Chupilko to Sergey Smolov
- Status changed from New to Resolved
The task has been moved to Verilog Translator project.
It is supposed, that Verilog design comes to Retrascope as completely instantiated model.