Support for module instances in Verilog descriptions
Updated by Sergey Smolov almost 2 years ago
- Detected in build changed from svn to master
- % Done changed from 0 to 100
- Assignee changed from Mikhail Chupilko to Sergey Smolov
- Status changed from New to Resolved
The task has been moved to Verilog Translator project.
It is supposed, that Verilog design comes to Retrascope as completely instantiated model.