support for non-zero-starting bit vector variables & signals
Re-calculate ranges for such signals & variables that are declared as non-zero-starting. For example, here we have the following Verilog code:
module bvsample(in, clk, out); input [2:1] in; input clk; output [1:0] out; reg [1:0] data; assign out = data; always @(posedge clk) begin if (in[2:2] == 1'b1) begin data <= 2'b11; end if (in[1:1] == 1'b0) begin data <= 2'b01; end end endmodule
Here in signal is non-zero-starting, i.e. it is declared in such a way, that it's least bit has number 1 but not 0. Since Verilog Translator returns BIT_VECTOR(2) data type for this signal reference, and non-zero-starting bit vectors are unsupported in Fortress, all the in signal references including ranges (like in the example above) should be transformed by shifting ranges to the declaration offset.