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2016-08-16T13:19:28Z
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Verilog Translator - Bug #7474: missing empty branches for 'if' statements
https://forge.ispras.ru/issues/7474?journal_id=27977
2016-08-16T13:19:28Z
Sergey Smolov
smolov@ispras.ru
<ul><li><strong>Status</strong> changed from <i>New</i> to <i>Resolved</i></li><li><strong>% Done</strong> changed from <i>0</i> to <i>100</i></li></ul><p>r422</p>
Verilog Translator - Bug #7474: missing empty branches for 'if' statements
https://forge.ispras.ru/issues/7474?journal_id=27978
2016-08-16T13:19:37Z
Sergey Smolov
smolov@ispras.ru
<ul><li><strong>Status</strong> changed from <i>Resolved</i> to <i>Verified</i></li></ul>
Verilog Translator - Bug #7474: missing empty branches for 'if' statements
https://forge.ispras.ru/issues/7474?journal_id=32566
2018-03-01T11:42:25Z
Alexander Kamkin
askamkin@gmail.com
<ul><li><strong>Status</strong> changed from <i>Verified</i> to <i>Closed</i></li></ul>