Bug #7474: missing empty branches for 'if' statements - Verilog Translator - Open-Source Projects

Bug #7474

missing empty branches for 'if' statements

Added by Sergey Smolov over 4 years ago. Updated about 3 years ago.

Status:

Closed

Priority:

Normal

Assignee:

Target version:

Start date:

08/16/2016

Due date:

% Done:

100%

Estimated time:

Detected in build:

svn

Platform:

Published in build:

Description

The tool skips empty 'else' branches for 'if' statements.

#1

Updated by Sergey Smolov over 4 years ago

Status changed from New to Resolved
% Done changed from 0 to 100

r422

#2

Updated by Sergey Smolov over 4 years ago

Status changed from Resolved to Verified

#3

Updated by Alexander Kamkin about 3 years ago

Status changed from Verified to Closed

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