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Task #6976
closedWiki update
Start date:
03/17/2016
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Published in build:
20161025
Description
Delete outdated info, add current models (HLDD) and analysis methods (model checking based).
Updated by Sergey Smolov over 8 years ago
- Status changed from New to Resolved
- % Done changed from 0 to 100
Add information about Verilog-related engines (other mentioned above are already added).
Updated by Sergey Smolov over 8 years ago
- Status changed from Resolved to Verified
Updated by Sergey Smolov almost 8 years ago
- Status changed from Verified to Closed
- Detected in build changed from svn to master
- Published in build set to 20161025
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