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Bug #6892

support for non-zero starting bitvectors

Added by Sergey Smolov almost 4 years ago. Updated over 3 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Engine (Parser)
Target version:
Start date:
02/24/2016
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
20161025

History

#1

Updated by Sergey Smolov almost 4 years ago

  • Status changed from New to Open
  • % Done changed from 0 to 50

Fixed for VHDL designs in cc972824.

#2

Updated by Sergey Smolov almost 4 years ago

  • Target version changed from 0.1 to 0.2
#3

Updated by Sergey Smolov over 3 years ago

For Verilog designs the following should be done: represent [max:min] vectors as [0:max-min] vectors and add related SHIFT meta-information that should be interpreted
upon NodeOperation objects construction.

#4

Updated by Sergey Smolov over 3 years ago

  • Status changed from Open to Resolved
  • % Done changed from 50 to 100

Done for Verilog designs in f7fdaa6d.

#5

Updated by Sergey Smolov over 3 years ago

  • Status changed from Resolved to Verified
  • Detected in build changed from svn to master
#6

Updated by Sergey Smolov over 3 years ago

  • Status changed from Verified to Closed
  • Published in build set to 20161025

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