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Task #6431

descriptor for (VHDL) variables & signals

Added by Sergey Smolov about 4 years ago. Updated over 3 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Engine (Parser)
Target version:
Start date:
11/13/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
0.2.1

Description

Implement a descriptor that keeps values of all the attributes of VHDL variable/signal.
All the other auxiliary data that is somehow connected with variable could also be added to this descriptor.

History

#1

Updated by Sergey Smolov about 4 years ago

  • Status changed from New to Open

Will be implemented on the base of VariableData class

#2

Updated by Sergey Smolov about 4 years ago

  • Status changed from Open to Resolved
  • % Done changed from 0 to 100

r2603

#3

Updated by Sergey Smolov over 3 years ago

  • Status changed from Resolved to Closed
  • Published in build set to 0.2.1

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