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Task #6368

Ranged assignment merge

Added by Mikhail Lebedev almost 5 years ago. Updated over 4 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
-
Target version:
Start date:
10/26/2015
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Published in build:
0.2.1

Description

Multiple sequential ranged assignments are needed to be merged into a single assignment.
For example (b10 itc design):

v_out : out bit_vector(3 downto 0)
...
v_out(0) <= voto0 ;
v_out(1) <= voto1 ;
v_out(2) <= voto2 ;
v_out(3) <= voto3 ;

This can be converted into the concatenation of bits:
v_out <= voto3 & voto2 & voto1 & voto0;

Something like:
v_out(0) <= voto0 ;
v_out(3) <= voto3 ;
is converted into:
v_out <= voto3 & v_out(2 downto 1) & voto0;

etc.

History

#1

Updated by Sergey Smolov almost 5 years ago

  • Category set to 127
  • Status changed from New to Open
  • Target version set to 0.1
#2

Updated by Sergey Smolov almost 5 years ago

  • Status changed from Open to Resolved
  • % Done changed from 0 to 100

Done in r2548.

Note that basic blocks in CGAA model now contain only concurrent (non-blocking) assignments.

#3

Updated by Mikhail Lebedev almost 5 years ago

  • Category deleted (127)
  • Status changed from Resolved to Verified
  • Target version deleted (0.1)
  • % Done changed from 100 to 0
#4

Updated by Sergey Smolov almost 5 years ago

  • Target version set to 0.1
#5

Updated by Sergey Smolov over 4 years ago

  • Status changed from Verified to Closed
  • Published in build set to 0.2.1

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