src/test/verilog/adder/adder4_testbench.v: wrong CFG model
The Verilog parser generates incorrect CFG model for adder4_testbench.v file.
Please look at GraphML representation of CFG model which was generated with disabled backends. This graph does not contain BasicBock node for "a = a + 1" assignment.
Note that this bug can be reproduced at revision 1639, when the last your change was made.