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Bug #6362
closedsrc/test/verilog/adder/adder4_testbench.v: wrong CFG model
Start date:
10/21/2015
Due date:
% Done:
0%
Estimated time:
Detected in build:
svn
Platform:
Published in build:
Description
The Verilog parser generates incorrect CFG model for adder4_testbench.v file.
Please look at GraphML representation of CFG model which was generated with disabled backends. This graph does not contain BasicBock node for "a = a + 1" assignment.
Note that this bug can be reproduced at revision 1639, when the last your change was made.
Files
Updated by Sergey Smolov almost 9 years ago
- Status changed from New to Rejected
This bug disappears at the new CFG inner representation.
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