Bug #6355: src/test/verilog/fifo/fifo_testbench.v: NullPointerException - Verilog Translator - Open-Source Projects

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Bug #6355

closed

src/test/verilog/fifo/fifo_testbench.v: NullPointerException

Added by Sergey Smolov over 8 years ago. Updated about 6 years ago.

Status:

Closed

Priority:

High

Assignee:

Alexander Kamkin

Target version:

0.1

Start date:

10/16/2015

Due date:

% Done:

Estimated time:

Detected in build:

svn

Platform:

Published in build:

Description

While running VerilogPrinter on src/test/verilog/fifo/fifo_testbench.v the following error appears:

Including file 'src/test/verilog/fifo/fifo_testbench.v'
java.lang.NullPointerException
    at ru.ispras.fortress.data.types.bitvector.BitVector.notNullCheck(BitVector.java:772)
    at ru.ispras.fortress.data.types.bitvector.BitVector.valueOf(BitVector.java:535)
    at ru.ispras.verilog.parser.model.basis.Literal.getBitVector(Literal.java:222)
    at ru.ispras.verilog.parser.model.basis.Literal.getValue(Literal.java:356)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_primary(VerilogTreeBuilder.java:7296)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:7146)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_task_statement(VerilogTreeBuilder.java:5031)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4633)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:6057)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4737)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3600)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:958)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:634)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:440)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:382)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:216)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:220)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:231)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:235)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:120)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:46)