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Task #5689

closed

implement test-to-Verilog printer

Added by Sergey Smolov about 9 years ago. Updated over 7 years ago.

Status:
Closed
Priority:
High
Assignee:
Category:
Engine (Printer)
Target version:
Start date:
03/05/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:
20161025

Description

The printer should generate Verilog testbenches that can be simulated using ModelSim or Icarus simulator.

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