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Task #5689

closed

implement test-to-Verilog printer

Added by Sergey Smolov almost 10 years ago. Updated about 8 years ago.

Status:
Closed
Priority:
High
Assignee:
Sergey Smolov
Category:
Engine (Printer)
Target version:
0.2
Start date:
03/05/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:
20161025

Description

The printer should generate Verilog testbenches that can be simulated using ModelSim or Icarus simulator.

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 #1

Updated by Sergey Smolov almost 10 years ago

  • Subject changed from [test][printer][verilog] implement test-to-Verilog printer to implement test-to-Verilog printer
  • Category set to Engine (Printer)
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 #2

Updated by Sergey Smolov almost 9 years ago

  • Target version changed from 0.1 to 0.2
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 #3

Updated by Sergey Smolov over 8 years ago

  • Assignee changed from Igor Melnichenko to Sergey Smolov
  • Priority changed from Normal to High
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 #4

Updated by Sergey Smolov over 8 years ago

  • Status changed from New to Open
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 #5

Updated by Sergey Smolov over 8 years ago

  • Status changed from Open to Resolved
  • % Done changed from 0 to 100

Done in a8012d86.

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 #6

Updated by Sergey Smolov about 8 years ago

  • Status changed from Resolved to Closed
  • Detected in build changed from svn to master
  • Published in build set to 20161025
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