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Task #5688

closed

implement test-to-VHDL printer

Added by Sergey Smolov almost 10 years ago. Updated over 9 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Igor Melnichenko
Category:
Engine (Printer)
Target version:
0.1
Start date:
03/05/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
20150701

Description

The printer should generate VHDL testbenchs that can be simulated using ModelSim or GHDL simulator.

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 #1

Updated by Sergey Smolov almost 10 years ago

  • Subject changed from [test][printer][vhdl] implement testbench-to-VHDL printer to [test][printer][vhdl] implement test-to-VHDL printer
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 #2

Updated by Sergey Smolov almost 10 years ago

  • Subject changed from [test][printer][vhdl] implement test-to-VHDL printer to implement test-to-VHDL printer
  • Category set to 67
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 #3

Updated by Igor Melnichenko over 9 years ago

  • Status changed from New to Open
  • % Done changed from 0 to 50

Errors in currently generated testbenches are gathered.

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 #4

Updated by Igor Melnichenko over 9 years ago

  • Status changed from Open to Resolved
  • % Done changed from 50 to 100
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 #5

Updated by Sergey Smolov over 9 years ago

  • Status changed from Resolved to Verified
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 #6

Updated by Sergey Smolov over 9 years ago

  • Status changed from Verified to Closed
  • Published in build set to 20150701
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