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Task #5683

STD_LOGIC/STD_ULOGIC processing

Added by Sergey Smolov over 4 years ago. Updated over 3 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Engine (Parser)
Target version:
Start date:
03/04/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
0.2.1

Description

The signals of STD_LOGIC/STD_ULOGIC now are modelled as DataType.BOOLEAN variables.

If this is incorrect (in fact, we have 9-sign logic at VHDL), the corresponding processing procedure should be implemented (see corresponding TODOs).

History

#1

Updated by Sergey Smolov over 4 years ago

  • Subject changed from [vhdl][parser][cfg] STD_LOGIC/STD_ULOGIC processing to STD_LOGIC/STD_ULOGIC processing
  • Category set to 64
#2

Updated by Sergey Smolov over 3 years ago

  • Status changed from New to Resolved
  • % Done changed from 0 to 100
  • Published in build set to 0.2.1
#3

Updated by Sergey Smolov over 3 years ago

  • Status changed from Resolved to Closed

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