Task #5651: Translate logic operation results into Boolean expressions - Verilog Translator - Open-Source Projects

Task #5651

Translate logic operation results into Boolean expressions

Added by Sergey Smolov about 6 years ago. Updated about 3 years ago.

Status:

Closed

Priority:

Normal

Assignee:

Target version:

Start date:

02/24/2015

Due date:

% Done:

100%

Estimated time:

Detected in build:

svn

Published in build:

r399

Description

See Literal & StandardIntegerOperations classes.

#1

Updated by Sergey Smolov about 6 years ago

Status changed from New to Open

#2

Updated by Sergey Smolov about 6 years ago

Status changed from Open to Resolved
% Done changed from 0 to 100
Published in build set to r399

#3

Updated by Sergey Smolov over 4 years ago

Status changed from Resolved to Verified

#4

Updated by Alexander Kamkin about 3 years ago

Status changed from Verified to Closed

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