Published in build:
- Subject changed from [project] extend HDL test suite to extend HDL test suite
- Category set to Test Suite
Check samples of asynchronous Verilog designs here: async.org.uk
Keywords: Tech report towards asynchronous power management
Look at synthagate examples coming with Decider.
- Target version changed from 0.1 to 0.2
- Detected in build changed from svn to master
- Target version changed from 0.2 to 1.0
- Status changed from New to Resolved
- % Done changed from 0 to 100
ITC99 designs are added in ab8526a7.
Some perspective benchmarks are stored in the internal sub-project.
- Status changed from Resolved to Verified
- Published in build set to 1.1.1-beta-190722
- Status changed from Verified to Closed
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