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Task #5588

extend HDL test suite

Added by Sergey Smolov over 4 years ago. Updated over 1 year ago.

Status:
Verified
Priority:
Normal
Assignee:
Category:
Test Suite
Target version:
Start date:
01/28/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:

Description

Extend a set of HDL (Verilog. VHDL) designs that are used as project test suite.

The collection of open-source benchmarks is available here: http://ddd.fit.cvut.cz/prj/Benchmarks/

History

#1

Updated by Sergey Smolov about 4 years ago

  • Subject changed from [project] extend HDL test suite to extend HDL test suite
  • Category set to Test Suite
#2

Updated by Sergey Smolov about 4 years ago

Check samples of asynchronous Verilog designs here: async.org.uk

Keywords: Tech report towards asynchronous power management

#3

Updated by Sergey Smolov about 4 years ago

Look at synthagate examples coming with Decider.

#4

Updated by Sergey Smolov about 3 years ago

  • Target version changed from 0.1 to 0.2
#5

Updated by Sergey Smolov over 2 years ago

  • Detected in build changed from svn to master
#6

Updated by Sergey Smolov over 1 year ago

  • Target version changed from 0.2 to 1.0
#7

Updated by Sergey Smolov over 1 year ago

  • Status changed from New to Resolved
  • % Done changed from 0 to 100

ITC99 designs are added in ab8526a7.
Some perspective benchmarks are stored in the internal sub-project.

#8

Updated by Sergey Smolov over 1 year ago

  • Status changed from Resolved to Verified

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