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Task #5578
closed[verilog][parser][cfg] add support of multiple assignments
Start date:
01/26/2015
Due date:
% Done:
0%
Estimated time:
Detected in build:
svn
Published in build:
20150307
Description
Add support of "multiple assignments" that are of the following form:
{x,y,z} = w;
Such assignments should be splitted into simple concurrent (non-blocking) assignments with taking defined variables' order into account.
The result of "multiple expression" (of the above form) processing should be like:
x = bvextract (w, offset_x);
y = bvextract (w, offset_y);
z = bvextract (w, offset_z);
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