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Task #5578

[verilog][parser][cfg] add support of multiple assignments

Added by Sergey Smolov over 5 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
Normal
Category:
-
Target version:
Start date:
01/26/2015
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Published in build:
20150307

Description

Add support of "multiple assignments" that are of the following form:

{x,y,z} = w;

Such assignments should be splitted into simple concurrent (non-blocking) assignments with taking defined variables' order into account.
The result of "multiple expression" (of the above form) processing should be like:

x = bvextract (w, offset_x);
y = bvextract (w, offset_y);
z = bvextract (w, offset_z);

History

#1

Updated by Sergey Smolov over 5 years ago

Don't forget about commented code parts (both at VerilogCfgBuilder and VerilogFiles classes).

#2

Updated by Mikhail Chupilko over 5 years ago

src/test/verilog/fifo_mod/fifo.v --target efsm

#3

Updated by Mikhail Chupilko over 5 years ago

  • Status changed from New to Open

Partially solved in r1513

#4

Updated by Mikhail Chupilko over 5 years ago

  • Status changed from Open to Resolved

Multiple assignments are supported. Being the only place to analyze such constructions, the method parseAssignment() was improved.

#5

Updated by Sergey Smolov over 5 years ago

  • Status changed from Resolved to Closed
  • Published in build set to 20150307

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