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Task #5569

support process variable declarations

Added by Sergey Smolov almost 5 years ago. Updated over 4 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Engine (Parser)
Target version:
Start date:
01/22/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
20150701

Related issues

Related to Retrascope - Task #5609: make process-local variables be efsm-model-globalRejected02/11/2015

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#1

Updated by Sergey Smolov almost 5 years ago

  • Subject changed from [vhdl][cfg][parser] support process variable declarations to support process variable declarations
  • Category set to 64
#2

Updated by Sergey Smolov almost 5 years ago

  • Status changed from New to Open
#3

Updated by Sergey Smolov almost 5 years ago

Here is an answer from Zamia team:

Среда, хранящая объекты называется IGContainer. Вот у меня пример был

tl = Toplevel(DMUID.parse("WORK.TB"), None)
module = project.getIGM().findModule(tl)

from org.zamia.instgraph import IGObject
import org.zamia.instgraph.IGObject.IGObjectCat
import org.zamia.instgraph.IGObject.OIDir

printf(str(module.findChild("PROC1")) + " objects are: %s", ','.join([str(l.getId()) for l in module.findChild("PROC1").getContainer().localItems()]))

module = project.getIGM().findModule(module.findChild("DUT").getSignature());
printf(str(module) + " ports are: %s", ','.join([str(l.getId()) for l in module.getContainer().getInterfaceList() if isinstance(l, org.zamia.instgraph.IGObject) and l.getCat() == IGObject.IGObjectCat.SIGNAL]))
printf(str(module) + " objects are: %s", ','.join([str(l.getId()) for l in module.getContainer().localItems()]))
printf(str(module) + " signals are: %s", ','.join([str(l.getId()) for l in module.getContainer().localItems() if isinstance(l, org.zamia.instgraph.IGObject) and l.getCat() == IGObject.IGObjectCat.SIGNAL]))

Для такой штуки

library CLASS, IEEE;
use IEEE.STD_LOGIC_1164.all;

entity GATE_LEVEL is
    port (A, B, C, D: STD_ULOGIC;
        Z: out STD_ULOGIC 
    ); 
end entity; 

library CLASS, IEEE;
use IEEE.STD_LOGIC_1164.all;

entity PARTITION is 
    port (A, B, C: STD_ULOGIC;
        Z: out STD_ULOGIC
    );
end entity; 

architecture ARCH of PARTITION is 
    signal Az: STD_ULOGIC; 
begin 
    A: entity CLASS.AN2 port map (A, B, Az); 
    B: entity CLASS.AN2 port map (Az, C, Z); 
end architecture; 

architecture Arch of GATE_LEVEL is
    signal Az: STD_ULOGIC;
    signal Bz: STD_ULOGIC;
    constant M: STD_ULOGIC := '1'; 
begin 
    G1: entity OR2 port map (A, B, Az);
    P1: entity PARTITION port map (Az, C, D, Z);
    P2: entity PARTITION port map (Az, C, D, Z);
    G3: entity OR2 port map (A, B, Az);
end architecture; 

entity TB is end entity; 

library IEEE;
use IEEE.STD_LOGIC_1164.all;

architecture ARCH of TB is
    signal a_sig, B_sig, C_sig, D_sig, Z_sig: STD_ULOGIC;
begin
    DUT: entity GATE_LEVEL port map (a_sig, B_sig, C_sig, D_sig, Z_sig);

    PROC1: process 
        variable DUMMY1: BIT;
        constant DUMMY2: BIT;
    begin
        a_sig <= '1';
        B_sig <= '1';
        c_sig <= '1';
        d_sig <= '1';
        wait for 10 ns;
        a_sig <= '1';
        B_sig <= '0';
        a_sig <= '1';
        B_sig <= '0';
        wait for 10 ns;
        wait;
    end process;
end architecture;

И выдаёт от вот такое

process (id=PROC1) objects are: DUMMY1,DUMMY2
IGModule(duuid=WORK.GATE_LEVEL(ARCH)) ports are: A,B,C,D,Z
IGModule(duuid=WORK.GATE_LEVEL(ARCH)) objects are: A,B,C,D,Z,AZ,BZ,M
IGModule(duuid=WORK.GATE_LEVEL(ARCH)) signals are: A,B,C,D,Z,AZ,BZ
<pre>

То есть module.getContainer().localItems() выдаёт то что вы просите. 

У объекта есть категория, которую я проверяю если хочу отобрать только сигналы, отбросив константы

l.getCat() == IGObject.IGObjectCat.SIGNAL

и направление, которое тоже можно при необходимости проверить igOpObject.getDirection() == IGObject.OIDir.OUT

Пример распечатывает содержимое architecture и process.
#4

Updated by Sergey Smolov almost 5 years ago

  • Status changed from Open to Resolved
  • % Done changed from 0 to 100

r1749

#5

Updated by Sergey Smolov almost 5 years ago

  • Status changed from Resolved to Verified
#6

Updated by Sergey Smolov over 4 years ago

  • Status changed from Verified to Closed
  • Published in build set to 20150701

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