Actions
Task #5549
closed[vhdl][cfg][parser] add support of instantiation
Start date:
01/12/2015
Due date:
% Done:
100%
Estimated time:
Detected in build:
svn
Published in build:
20150307
Description
Implement a support in modules' instances at the CFG level.
Elaborate VHDL/Verilog designs from project test suite, that contain instances.
Actions