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Task #5549

closed

[vhdl][cfg][parser] add support of instantiation

Added by Sergey Smolov over 9 years ago. Updated about 9 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Sergey Smolov
Category:
-
Target version:
0.2
Start date:
01/12/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
20150307

Description

Implement a support in modules' instances at the CFG level.
Elaborate VHDL/Verilog designs from project test suite, that contain instances.

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 #1

Updated by Sergey Smolov about 9 years ago

  • Status changed from New to Open
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 #2

Updated by Sergey Smolov about 9 years ago

  • Subject changed from [cfg] add support of instantiation to [vhdl][cfg][parser] add support of instantiation
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 #3

Updated by Sergey Smolov about 9 years ago

  • Status changed from Open to Resolved
  • % Done changed from 0 to 100
  • Published in build set to r1509
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 #4

Updated by Sergey Smolov about 9 years ago

  • Status changed from Resolved to Closed
  • Published in build changed from r1509 to 20150307
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