Retrascope

2014.12.10 15:58:39.930. INFO: Retrascope is starting
Running: verilog-parser
Options: {args=src/test/verilog/ram/ram.v --target efsm, v=[src/test/verilog/ram/ram.v]}
Including file 'src/test/verilog/ram/ram.v'
2014.12.10 15:58:40.179. INFO: Start observing module ram.
2014.12.10 15:58:40.180. INFO: add variable clk [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
2014.12.10 15:58:40.181. INFO: add variable rst [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
2014.12.10 15:58:40.181. INFO: add variable val_rd [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
2014.12.10 15:58:40.181. INFO: add variable val_wr [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
2014.12.10 15:58:40.181. INFO: add variable addr_in [(BIT_VECTOR 2)] (Data[type=(BIT_VECTOR 2), value=uninitialized]) to module ram.
2014.12.10 15:58:40.182. INFO: add variable data_in [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.
2014.12.10 15:58:40.182. INFO: add variable val_out [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
2014.12.10 15:58:40.182. INFO: add variable data_out [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.
2014.12.10 15:58:40.182. INFO: add variable is_ready [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
2014.12.10 15:58:40.183. INFO: add variable mem0 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.
2014.12.10 15:58:40.183. INFO: add variable mem1 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.
2014.12.10 15:58:40.183. INFO: add variable mem2 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.
2014.12.10 15:58:40.183. INFO: add variable mem3 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.
2014.12.10 15:58:40.183. INFO: add variable result [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.
2014.12.10 15:58:40.184. INFO: add variable state [(BIT_VECTOR 2)] (Data[type=(BIT_VECTOR 2), value=uninitialized]) to module ram.
2014.12.10 15:58:40.188. INFO: add variable RAM_IDLE [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
2014.12.10 15:58:40.192. INFO: add variable RAM_READ [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
2014.12.10 15:58:40.192. INFO: add variable RAM_WRITE [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
2014.12.10 15:58:40.193. INFO: add variable RAM_RESULT [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.
Storing: cfg

Running: cfg-cgaa-transformer
Options: {args=src/test/verilog/ram/ram.v --target efsm, cfg=<cfg>}
Storing: cgaa

Running: cgaa-efsm-transformer
Options: {args=src/test/verilog/ram/ram.v --target efsm, cgaa=<cgaa>}
2014.12.10 15:58:40.218. ERROR: The exception has been encountered: java.lang.UnsupportedOperationException: (BVAND (BVNOT rst) val_rd).
at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.getBinaryOperationEvent(CgaaStateExprVisitor.java:241)
at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.getOperationEvent(CgaaStateExprVisitor.java:185)
at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.getEvent(CgaaStateExprVisitor.java:168)
at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.onCaseBegin(CgaaStateExprVisitor.java:152)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitCase(CfgWalker.java:252)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:145)
at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:116)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitSwitch(CfgWalker.java:235)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:151)
at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:116)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitCase(CfgWalker.java:253)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:145)
at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:116)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitSwitch(CfgWalker.java:235)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:151)
at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:116)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitSource(CfgWalker.java:219)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:157)
at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:116)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitCfg(CfgWalker.java:210)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitProcess(CfgWalker.java:201)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitModule(CfgWalker.java:185)
at ru.ispras.retrascope.model.cfg.CfgWalker.visitCfgModel(CfgWalker.java:172)
at ru.ispras.retrascope.model.cfg.CfgWalker.start(CfgWalker.java:92)
at ru.ispras.retrascope.engine.cfg.CfgEngine.start(CfgEngine.java:133)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:199)
at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:199)
at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:117)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:329)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:350)