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Task #4872

closed

[verilog][translator] Проработать интерфейс backend'а транслятора с Verilog

Added by Alexander Kamkin almost 10 years ago. Updated almost 10 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Alexander Kamkin
Category:
-
Target version:
0.1
Start date:
04/30/2014
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Published in build:

Description

  1. Проработать интерфейс backend'а транслятора (обходчика AST).
  2. Описать в Вики интерфейс backend'а и механизмы добавления backend'а в транслятор.
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 #1

Updated by Alexander Kamkin almost 10 years ago

  • Status changed from New to Open
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 #2

Updated by Alexander Kamkin almost 10 years ago

  • Status changed from Open to Resolved

Интерфейс backend'a описан здесь (по ходу дела информация будет детализироваться):
http://forge.ispras.ru/projects/veritrans/wiki/Getting_Started

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 #3

Updated by Alexander Kamkin almost 10 years ago

  • Status changed from Resolved to Closed
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