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Task #4872

[verilog][translator] Проработать интерфейс backend'а транслятора с Verilog

Added by Alexander Kamkin over 5 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
Normal
Category:
-
Target version:
Start date:
04/30/2014
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Published in build:

Description

  1. Проработать интерфейс backend'а транслятора (обходчика AST).
  2. Описать в Вики интерфейс backend'а и механизмы добавления backend'а в транслятор.

History

#1

Updated by Alexander Kamkin over 5 years ago

  • Status changed from New to Open
#2

Updated by Alexander Kamkin over 5 years ago

  • Status changed from Open to Resolved

Интерфейс backend'a описан здесь (по ходу дела информация будет детализироваться):
http://forge.ispras.ru/projects/veritrans/wiki/Getting_Started

#3

Updated by Alexander Kamkin over 5 years ago

  • Status changed from Resolved to Closed

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