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Task #4075
closedSupport for the case equality/inequality (=== and !==) operators
Start date:
04/04/2013
Due date:
% Done:
100%
Estimated time:
Detected in build:
svn
Published in build:
0.2
Description
Verilog has two types of equility/inequality operators: (1) logical equality/inequality and (2) case equality/inequality. The only difference is in processing of X and Z values (4-valued logic is in use). The logical operators return X when comparing something with X or Z, while the case operators cannot return X (only 0 or 1).
I guess VHDL has something like that (as far as I know, it uses 9-valued logic).
My suggestion is to add EQCASE and NOTEQCASE operators to EVerilogOperation and implement them in the same way as the logical analogs have done. In fact, the SMT core supports only 2-valued bit vectors.
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