Support for the case equality/inequality (=== and !==) operators
Verilog has two types of equility/inequality operators: (1) logical equality/inequality and (2) case equality/inequality. The only difference is in processing of
Z values (4-valued logic is in use). The logical operators return
X when comparing something with
Z, while the case operators cannot return
X (only 0 or 1).
I guess VHDL has something like that (as far as I know, it uses 9-valued logic).
My suggestion is to add
NOTEQCASE operators to
EVerilogOperation and implement them in the same way as the logical analogs have done. In fact, the SMT core supports only 2-valued bit vectors.