Project

General

Profile

Task #4075

Support for the case equality/inequality (=== and !==) operators

Added by Alexander Kamkin almost 8 years ago. Updated over 7 years ago.

Status:
Closed
Priority:
Normal
Category:
-
Target version:
Start date:
04/04/2013
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
0.2

Description

Verilog has two types of equility/inequality operators: (1) logical equality/inequality and (2) case equality/inequality. The only difference is in processing of X and Z values (4-valued logic is in use). The logical operators return X when comparing something with X or Z, while the case operators cannot return X (only 0 or 1).

I guess VHDL has something like that (as far as I know, it uses 9-valued logic).

My suggestion is to add EQCASE and NOTEQCASE operators to EVerilogOperation and implement them in the same way as the logical analogs have done. In fact, the SMT core supports only 2-valued bit vectors.

History

#1

Updated by Alexander Kamkin almost 8 years ago

  • Target version set to 0.1
#2

Updated by Sergey Smolov almost 8 years ago

  • Status changed from New to Resolved
  • Assignee changed from Sergey Smolov to Alexander Kamkin

Операции EQCASE, NOTEQCASE добавлены. Транслируются в те же операции SMT-LIB, что и операции EQ, NOTEQ соответственно.

r66

#3

Updated by Sergey Smolov over 7 years ago

  • % Done changed from 0 to 100
  • Published in build set to 0.2
#4

Updated by Sergey Smolov over 7 years ago

  • Status changed from Resolved to Closed

Also available in: Atom PDF