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Task #4069

Decomposition of the BVSHL into BVLSHL and BVASHL

Added by Alexander Kamkin almost 8 years ago. Updated over 7 years ago.

Status:
Closed
Priority:
Normal
Category:
-
Target version:
Start date:
04/04/2013
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
0.2

Description

I know that the left arithmetic shift works as the left logical shift, but in Verilog two operators <<< and << exists. To distinguish them, I suggest splitting BVSHL into BVLSHL and BVASHL (as it is done for the right shift operator).

P.S. BVLSHL and BVASHL processing may be the same.

History

#1

Updated by Alexander Kamkin almost 8 years ago

  • Target version set to 0.1
#2

Updated by Sergey Smolov almost 8 years ago

  • Status changed from New to Resolved
  • Assignee changed from Sergey Smolov to Alexander Kamkin

Идентификаторы BVLSHL и BVASHL добавил, обе транслируются в один и тот же оператор SMT-LIB

r65

#3

Updated by Sergey Smolov over 7 years ago

  • % Done changed from 0 to 100
  • Published in build set to 0.2
#4

Updated by Sergey Smolov over 7 years ago

  • Status changed from Resolved to Closed

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