Task #1270
closed
Совместное использование с SystemVerilog
Added by Alexander Kamkin over 13 years ago.
Updated about 13 years ago.
Description
Примеры совместного использования C++TESK с моделями/ассерциями/покрытиями SystemVerilog.
Рабочий пример использования связки C++TESK+SV (модель, покрытия; утверждения реализуются аналогично покрытиям) есть в mauhub/branches/cpptesk.
Он сделан под VCS.
- Assignee changed from Alexander Kamkin to Mikhail Chupilko
It would be useful to have a simple example (with comments and/or description) on using C++TESK and SystemVerilog together.
- Status changed from New to Open
The example was added in r360 of C++TESK Hardware Edition. It should work as it is based on mauhub cpptesk-branch but there is a little problem. The linker can not resolve link to testreg in spite of the fact that the working makefiles have been copied from mauhub project and have not been modified greatly.
- Status changed from Open to Resolved
The example was corrected in r363 of C++TESK HE and now it works. The problem with linker was as follows. When using VCS, we have to use VCS's linker to make executable simv file containing the implementation and test system. For some reasons the linker can not resolve link to test_registry in netfsm/lib/src/utils/testregpp.cpp file if a function from this file (say startScenario_cpp_TestRegistry()) is used. The problem hasn't been solved by now but it was avoided by means of coping fragment of startScenario_cpp_TestRegistry function inside of vpi_systf.cpp.
Some additional code comments of the test system would make it more convenient for the users.
- Target version set to 1.0
- Status changed from Resolved to Feedback
It would be nice to have a wiki paper on using C++TESK together with SystemVerilog.
Can't help agreeing :) Ok, I'll make it.
- Status changed from Feedback to Resolved
- Assignee changed from Mikhail Chupilko to Alexander Kamkin
- Status changed from Resolved to Closed
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