Совместное использование с SystemVerilog
Примеры совместного использования C++TESK с моделями/ассерциями/покрытиями SystemVerilog.
#3 Updated by Mikhail Chupilko over 7 years ago
- Status changed from New to Open
The example was added in r360 of C++TESK Hardware Edition. It should work as it is based on mauhub cpptesk-branch but there is a little problem. The linker can not resolve link to testreg in spite of the fact that the working makefiles have been copied from mauhub project and have not been modified greatly.
#4 Updated by Mikhail Chupilko over 7 years ago
- Status changed from Open to Resolved
The example was corrected in r363 of C++TESK HE and now it works. The problem with linker was as follows. When using VCS, we have to use VCS's linker to make executable simv file containing the implementation and test system. For some reasons the linker can not resolve link to test_registry in netfsm/lib/src/utils/testregpp.cpp file if a function from this file (say startScenario_cpp_TestRegistry()) is used. The problem hasn't been solved by now but it was avoided by means of coping fragment of startScenario_cpp_TestRegistry function inside of vpi_systf.cpp.
Some additional code comments of the test system would make it more convenient for the users.