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Bug #10513

macOS related line endings at Verilog modules

Added by Sergey Smolov 2 months ago. Updated 2 months ago.

Status:
New
Priority:
Normal
Target version:
Start date:
10/04/2020
Due date:
% Done:

0%

Estimated time:
Detected in build:
git
Platform:
Published in build:

Description

Verilog Translator does not support macOS related line endings ('\r') at Verilog modules. Is it ok for the tool?

History

#1

Updated by Sergey Smolov 2 months ago

  • Target version set to 0.1

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