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Bug #10513

open

macOS related line endings at Verilog modules

Added by Sergey Smolov about 4 years ago. Updated about 4 years ago.

Status:
New
Priority:
Normal
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
10/04/2020
Due date:
% Done:

0%

Estimated time:
Detected in build:
git
Platform:
Published in build:

Description

Verilog Translator does not support macOS related line endings ('\r') at Verilog modules. Is it ok for the tool?

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 #1

Updated by Sergey Smolov about 4 years ago

  • Target version set to 0.1
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