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Bug #10512

ADDA162H90A_atop.v line 120:47 mismatched input ':' expecting RPAREN

Added by Sergey Smolov 2 months ago. Updated 2 months ago.

Status:
New
Priority:
Normal
Target version:
Start date:
10/02/2020
Due date:
% Done:

0%

Estimated time:
Detected in build:
git
Platform:
Published in build:

Description

RROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\faraday\rtl\DSP\hdl\CODEC\FXADDA162H90A\ADDA162H90A_atop.v line 120:47 mismatched input ':' expecting RPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\faraday\rtl\DSP\hdl\CODEC\FXADDA162H90A\ADDA162H90A_atop.v line 157:47 mismatched input ':' expecting RPAREN
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 117:36 mismatched tree node: <mismatched token: [@2436,3042:3042=':',<19>,120:47], resync=$width(posedgedac_phase_check,400.00:500.00:900.00,0,> expecting <UP>
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 117:36 mismatched tree node: AST_ATTRIBUTES expecting <UP>
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 117:36 mismatched tree node: <unexpected: [@2444,3089:3089=')',<276>,120:94], resync=n_flag_dac_phase_overlape> expecting <UP>

Associated revisions

Revision 5f8c7dc7 (diff)
Added by Sergey Smolov 2 months ago

junit: uncomment tests are falling because of #10512

Signed-off-by: Sergey Smolov <>

History

#1

Updated by Sergey Smolov 2 months ago

To reproduce the bug, switch to bug10512 branch an run the ru.ispras.verilog.parser.VerilogIwlsTestSuite test suite

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