Bug #10336
Incorrect ranges in vhdl/plasma/reg_bank.vhd
Start date:
05/14/2020
Due date:
% Done:
100%
Estimated time:
Detected in build:
git
Platform:
Published in build:
Description
reg_bank
design in plasma contains the following array variable:
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0); variable tri_port_ram : ram_type;
In CFG model the data type of this variable is correct:
Variable[name=RAM_PROC.TRI_PORT_RAM, data=Data[type=(MAP LOGIC_INTEGER (BIT_VECTOR 32)), value=uninitialized]]
But the variable descriptor contains two ranges for it: 0:31, 0:31
This results in the following incorrect SMV-code:
VAR RAM_PROC_TRI_PORT_RAM : array 0..31 of array 0..31 of word[32];
One range is excessive.
Associated revisions
History
Updated by Sergey Smolov 8 months ago
- Target version set to 1.1
- Status changed from New to Resolved
- Category set to Engine (Parser)
Updated by Mikhail Lebedev 8 months ago
- % Done changed from 0 to 100
- Status changed from Resolved to Verified
Updated by Sergey Smolov 8 months ago
- Subject changed from Incorrect ranges in vhdl/plasma/reg_bank.vhdl to Incorrect ranges in vhdl/plasma/reg_bank.vhd
vhdl-parser: fix "wrong range num" bug (#10336)
Signed-off-by: Sergey Smolov <smolov@ispras.ru>