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Bug #10246

closed

ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found

Added by Sergey Smolov over 4 years ago. Updated over 4 years ago.

Status:
Rejected
Priority:
Normal
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
04/09/2020
Due date:
% Done:

0%

Estimated time:
Detected in build:
git
Platform:
Published in build:

Description

The tool takes 'lut_output.v' Verilog files as input, but reports it's absence.

ERROR: Module 'lut_output' has not been found
ERROR: [Internal] null
java.lang.IllegalArgumentException
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
    at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
    at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:126)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:397)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:231)
    at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
    at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_001(VerilogQuipTestSuite.java:355)

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