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Bug #10237

ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v'

Added by Sergey Smolov about 1 year ago. Updated 6 months ago.

Status:
Closed
Priority:
High
Assignee:
Alexey Danilov
Target version:
0.1
Start date:
04/08/2020
Due date:
% Done:

0%

Estimated time:
Detected in build:
git
Platform:
Published in build:
0.1.3-beta-201002

Description

The tool reports about cycle inclusion, but the described file does not contain includes at all.
Run ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2 to reproduce it.

#1

Updated by Alexey Danilov about 1 year ago

  • Status changed from New to Resolved
#2

Updated by Sergey Smolov 12 months ago

  • Status changed from Resolved to Verified
#3

Updated by Sergey Smolov 6 months ago

  • Published in build set to 0.1.3-beta-201002
  • Status changed from Verified to Closed

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