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Bug #10236

closed

efsm-test-generator hangs at opencores/mips16/data_mem.v

Added by Sergey Smolov over 4 years ago. Updated over 4 years ago.

Status:
Rejected
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Engine (Generator)
Target version:
1.1
Start date:
04/08/2020
Due date:
% Done:

0%

Estimated time:
Detected in build:
git
Platform:
Published in build:

Description

2020.04.04 13:47:13.604. INFO: Retrascope is starting
    2020.04.04 13:47:13.604. INFO: Running: verilog-parser

    2020.04.04 13:47:13.604. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, v=[/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v]}

    2020.04.04 13:47:13.648. INFO: Storing: cfg

    2020.04.04 13:47:13.648. INFO: Running: cfg-gadd-transformer

    2020.04.04 13:47:13.648. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, cfg=<cfg>}

    2020.04.04 13:47:13.773. INFO: Clock-like variables (CLV): data_mem.clk.
    2020.04.04 13:47:13.774. INFO: Storing: gadd

    2020.04.04 13:47:13.774. INFO: Running: gadd-efsm-transformer

    2020.04.04 13:47:13.774. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, gadd=<gadd>}

    2020.04.04 13:47:13.802. INFO: Execution path number: 264
    2020.04.04 13:47:13.802. INFO: ======================================
    2020.04.04 13:47:13.802. INFO: Transforming the process 'data_mem process'.
    2020.04.04 13:47:13.802. INFO: State-like variables: <none>.
    2020.04.04 13:47:13.802. INFO: Model states number: 1.
    2020.04.04 13:47:13.802. INFO: Model transitions number: 1.
    2020.04.04 13:47:13.802. INFO: ======================================
    2020.04.04 13:47:13.802. INFO: Transforming the process 'data_mem process (posedge of data_mem.clk)'.
    2020.04.04 13:47:13.802. INFO: State-like variables: <none>.
    2020.04.04 13:47:19.833. INFO: Model states number: 262.
    2020.04.04 13:47:19.833. INFO: Model transitions number: 519.
    2020.04.04 13:47:19.833. INFO: ======================================
    2020.04.04 13:47:19.833. INFO: Transforming the process 'data_mem process'.
    2020.04.04 13:47:19.833. INFO: State-like variables: <none>.
    2020.04.04 13:47:19.833. INFO: Model states number: 1.
    2020.04.04 13:47:19.833. INFO: Model transitions number: 1.
    2020.04.04 13:47:19.833. INFO: ======================================
    2020.04.04 13:47:19.833. INFO: The number of extracted models: 3.
    2020.04.04 13:47:19.833. INFO: The total number of states: 264.
    2020.04.04 13:47:19.834. INFO: The total number of transitions: 521.
    2020.04.04 13:47:19.834. INFO: ======================================
    2020.04.04 13:47:19.834. INFO: The initial state for data_mem process (40bc96d3): node=true phase=0
    2020.04.04 13:47:19.834. INFO: ======================================
    2020.04.04 13:47:19.834. INFO: The initial state for data_mem process (posedge of data_mem.clk) (6b3c814f): node=true phase=0
    2020.04.04 13:47:20.002. WARNING: Can't find resetting transition for data_mem process (posedge of data_mem.clk) (6b3c814f)
    2020.04.04 13:47:20.002. WARNING: The extracted EFSM is not single testable: data_mem process (posedge of data_mem.clk) (6b3c814f)
    2020.04.04 13:47:20.002. WARNING: The initial state is selected arbitrarily: node=true phase=0
    2020.04.04 13:47:20.002. INFO: ======================================
    2020.04.04 13:47:20.019. INFO: The initial state for data_mem process (1ef0e6ca): node=true phase=0
    2020.04.04 13:47:20.020. WARNING: Can't find resetting transition for data_mem process (1ef0e6ca)
    2020.04.04 13:47:20.020. WARNING: The extracted EFSM is not single testable: data_mem process (1ef0e6ca)
    2020.04.04 13:47:20.020. WARNING: The initial state is selected arbitrarily: node=true phase=0
    2020.04.04 13:47:20.020. INFO: ======================================
    2020.04.04 13:47:20.020. INFO: Storing: efsm

    2020.04.04 13:47:20.020. INFO: Running: cfg-cfginterface-extractor

    2020.04.04 13:47:20.020. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, cfg=<cfg>}

    2020.04.04 13:47:20.020. INFO: Storing: cfg-iface

    2020.04.04 13:47:20.020. INFO: Running: efsm-test-generator

    2020.04.04 13:47:20.020. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, efsm=<efsm>}

    2020.04.04 13:47:20.020. INFO: EFSM.TestGenerator: module data_mem: starting test generation
    2020.04.04 13:47:20.024. WARNING: The efsm can't be tested as a single one: data_mem process (posedge of data_mem.clk) (6b3c814f)
    2020.04.04 13:47:20.024. WARNING: The efsm can't be tested as a single one: data_mem process (1ef0e6ca)
    2020.04.04 13:47:20.024. WARNING: Wrong init value for 'data_mem.ram_addr': (BVEXTRACT 7 0 data_mem.mem_access_addr)
    2020.04.04 13:47:20.024. WARNING: The efsm can't be tested as a single one: data_mem process (posedge of data_mem.clk) (6b3c814f)
    2020.04.04 13:47:20.024. WARNING: The efsm can't be tested as a single one: data_mem process (1ef0e6ca)
    2020.04.04 13:47:20.027. WARNING: Wrong init value for 'data_mem.ram_addr': (BVEXTRACT 7 0 data_mem.mem_access_addr)
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 #1

Updated by Sergey Smolov over 4 years ago

  • Status changed from New to Rejected

Not actual.

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