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Bug #10214

ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module'

Added by Sergey Smolov 7 months ago. Updated 7 months ago.

Status:
Rejected
Priority:
Normal
Assignee:
Target version:
Start date:
04/06/2020
Due date:
% Done:

0%

Estimated time:
Detected in build:
git
Platform:
Published in build:

Description

ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\nut_000\nut_000_lut.v line 7:0 no viable alternative at input 'module'
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 30417:21 mismatched tree node: <unexpected: [@116916,240:245='module',<123>,7:0], resync=modulecarry_sum(sin,cin,sout,cout);inputsin;inputcin;outputsout;outputcout;> expecting AST_MODULE_ITEMS
ERROR: [Internal] null
java.lang.IllegalArgumentException
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
    at ru.ispras.verilog.parser.core.AbstractNode.add(AbstractNode.java:382)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:718)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:665)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:443)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:448)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:474)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:478)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:206)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
    at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_000(VerilogQuipTestSuite.java:302)

History

#1

Updated by Sergey Smolov 7 months ago

  • Assignee changed from Alexander Kamkin to Sergey Smolov
  • Status changed from New to Rejected

This crash was caused by missing 'endmodule' at Verilog. Rejected.

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