Bug #10195
Test test_12_04_02_4.v has an error.
Start date:
04/01/2020
Due date:
% Done:
100%
Estimated time:
Detected in build:
feature/error-module-checker
Platform:
Published in build:
0.1.3-beta-201002
Description
ERROR: Port 'udqm' has been declared two or more times in module 'sms_08b216t0'.
Associated revisions
History
Updated by Sergey Smolov 10 months ago
- Detected in build changed from git to feature/error-module-checker
- Target version set to 0.1
- Assignee set to Sergey Smolov
- Status changed from New to Open
Updated by Sergey Smolov 10 months ago
- % Done changed from 0 to 100
- Status changed from Open to Resolved
Updated by Sergey Smolov 4 months ago
- Published in build set to 0.1.3-beta-201002
- Status changed from Resolved to Closed
verilog: fix multiple declaration (#10195)
Signed-off-by: Sergey Smolov <smolov@ispras.ru>