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Bug #10195

Test test_12_04_02_4.v has an error.

Added by Alexey Danilov 4 months ago. Updated 4 months ago.

Status:
Resolved
Priority:
Normal
Assignee:
Target version:
Start date:
04/01/2020
Due date:
% Done:

100%

Estimated time:
Detected in build:
feature/error-module-checker
Platform:
Published in build:

Description

ERROR: Port 'udqm' has been declared two or more times in module 'sms_08b216t0'.

Associated revisions

Revision 9b4d40b3 (diff)
Added by Sergey Smolov 4 months ago

verilog: fix multiple declaration (#10195)

Signed-off-by: Sergey Smolov <>

History

#1

Updated by Sergey Smolov 4 months ago

  • Detected in build changed from git to feature/error-module-checker
  • Target version set to 0.1
  • Assignee set to Sergey Smolov
  • Status changed from New to Open
#2

Updated by Sergey Smolov 4 months ago

  • % Done changed from 0 to 100
  • Status changed from Open to Resolved

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