MicroTESK

MMU specifications look like they are written for a single core. That's OK and, I think, it should be so. However, it is unclear how to instantiate the caches and connects them with the cores, the main memory and each other in multi-core settings. There should be a kind of configuration.

The modeling library provides the following mechanisms.

CacheUnit's constructor has the next parameter, which is a reference to the next-level cache instance or the main memory (null if the next attribute is not specified):

public CacheUnit(..., final Buffer<? extends Struct<?>, A> next)

Also, CacheUnit implements the addNeighbor method that links the cache instance with the same-level ones:

public void addNeighbor(final CacheUnit<?, A> other)