Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692023-03-01T17:01:40ZOpen-Source Projects
Redmine Track Finding Tools for NICA MPD - Task #12203 (New): Кластеризация треков-кандидатов по заданным...https://forge.ispras.ru/issues/122032023-03-01T17:01:40ZAlexander Kamkinaskamkin@gmail.com
<p>Кластеризация треков-кандидатов по параметрам прямым и другим характеристикам.</p> Track Finding Tools for NICA MPD - Task #12202 (New): Конструирование признаков треков-кандидатов...https://forge.ispras.ru/issues/122022023-03-01T17:00:24ZAlexander Kamkinaskamkin@gmail.com
<p>Вывод параметров прямых и других характеристик (если нужно) для треков-кандидатов.</p> Veritool - Task #10507 (New): Introduce versions and close the resolved issueshttps://forge.ispras.ru/issues/105072020-10-01T07:46:56ZAlexander Kamkinaskamkin@gmail.com
<p>I suggest (1) introducing versions (0.1, 0.2, etc.) to group delivery files and (2) closing the resolved issues.</p> Veritool - Bug #10506 (Resolved): Veritool does not support escaped identifiershttps://forge.ispras.ru/issues/105062020-10-01T07:41:54ZAlexander Kamkinaskamkin@gmail.com
<p>Veritool does not support escaped identifiers, such as \begin (see the standard).</p> MicroTESK - Task #10193 (New): Cache instances configurationhttps://forge.ispras.ru/issues/101932020-04-01T07:23:10ZAlexander Kamkinaskamkin@gmail.com
<p>MMU specifications look like they are written for a single core. That's OK and, I think, it should be so. However, it is unclear how to instantiate the caches and connects them with the cores, the main memory and each other in multi-core settings. There should be a kind of configuration.</p>
<p>The modeling library provides the following mechanisms.</p>
<p><code>CacheUnit</code>'s constructor has the <code>next</code> parameter, which is a reference to the next-level cache instance or the main memory (<code>null</code> if the <code>next</code> attribute is not specified):</p>
<pre><code class="java syntaxhl" data-language="java"><span class="kd">public</span> <span class="nf">CacheUnit</span><span class="o">(...,</span> <span class="kd">final</span> <span class="nc">Buffer</span><span class="o"><?</span> <span class="kd">extends</span> <span class="nc">Struct</span><span class="o"><?>,</span> <span class="no">A</span><span class="o">></span> <span class="n">next</span><span class="o">)</span>
</code></pre>
<p>Also, <code>CacheUnit</code> implements the <code>addNeighbor</code> method that links the cache instance with the same-level ones:</p>
<pre><code class="java syntaxhl" data-language="java"><span class="kd">public</span> <span class="kt">void</span> <span class="nf">addNeighbor</span><span class="o">(</span><span class="kd">final</span> <span class="nc">CacheUnit</span><span class="o"><?,</span> <span class="no">A</span><span class="o">></span> <span class="n">other</span><span class="o">)</span>
</code></pre> Fortress - Bug #10177 (Feedback): TreeVisitor's SKIP status does not work as expectedhttps://forge.ispras.ru/issues/101772020-03-24T08:49:09ZAlexander Kamkinaskamkin@gmail.com
<p>When I call <code>setStatus(Status.SKIP)</code> in <code>onOperationBegin(node)</code>, I expect the visitor will not visit the node's children but will visit the node's neighbors.<br />However, the call skips visiting the neighbors.</p> MicroTESK - Bug #10136 (New): Comment for self checks differs from the othershttps://forge.ispras.ru/issues/101362020-02-25T14:51:38ZAlexander Kamkinaskamkin@gmail.com
<pre>
#==================================================================================================
# Test Case 0 (product.rb:27)
# Preparation
or t0, zero, zero
li t1, 0xaa1f0a7293a51583
li t3, 0xfffffffffffffffe
li t4, 0xfffffffffffffffe
# Stimulus
add t2, t1, t0
ori a0, t3, -434
xor t5, a0, t4
#==================================================================================================
# Self-Checks for Test Case 0
li sp, 0xaa1f0a7293a51583
bne sp, t2, fail
li sp, 0xfffffffffffffffe
bne sp, a0, fail
bne zero, t5, fail
</pre> MicroTESK - Bug #10124 (New): Double preparation of the same registerhttps://forge.ispras.ru/issues/101242020-02-18T15:27:23ZAlexander Kamkinaskamkin@gmail.com
<pre>
# Preparation
li a6, 0xfffffffffffffffe
li sp, 0xf0455f8f000e3ca0
or sp, zero, zero
li gp, 0x4da9d757a0275cb0
# Stimulus
add sp, sp, a6
sub gp, gp, sp
</pre> MicroTESK - Task #10122 (New): Template libraries for standard featureshttps://forge.ispras.ru/issues/101222020-02-13T15:25:44ZAlexander Kamkinaskamkin@gmail.com
<p>Some template features seem to be common for all ISAs, e.g.,</p>
<ol>
<li><code>riscv_base.rb</code>: constants <code>NAN</code>, <code>INF</code>, etc (IEEE 754);</li>
<li><code>riscv_base.rb</code>: data definition directives <code>.byte</code>, <code>.hword</code>, etc (GNU assembler).</li>
</ol>
<p>I suggest introducing template libraries such as</p>
<ol>
<li><code>float.rb</code> and</li>
<li><code>gnu.rb</code></li>
</ol>
<p>to avoid copy-paste.</p> MicroTESK - Task #10107 (New): Entry point specification in templateshttps://forge.ispras.ru/issues/101072020-02-11T12:39:03ZAlexander Kamkinaskamkin@gmail.com
<p>Currently, it is assumed (in the linker script printer, in particular) that the entry point is called <code>_start</code>.</p> MicroTESK - Task #10106 (New): Support %b as format's specifierhttps://forge.ispras.ru/issues/101062020-02-11T12:36:41ZAlexander Kamkinaskamkin@gmail.com
<p>Currently, we use <code>%s</code>; however, the nML specification requires <code>%b</code></p> MicroTESK - Bug #10061 (New): Buffers are now shared among all processing elementshttps://forge.ispras.ru/issues/100612020-01-23T08:22:05ZAlexander Kamkinaskamkin@gmail.com
<ol>
<li>By default, each buffer (unless it is memory mapped) is local.</li>
<li>To make a buffer global, one should write <code>shared</code> before the buffer declaration.</li>
<li>The memory plugin is not responsible for resetting memory- and register-mapped buffers.</li>
</ol>
<p>Classes to be modified: <code>Model</code>, <code>ProcessingElement</code>, <code>MmuPlugin</code>, etc.</p> MicroTESK for RISC-V - Task #9978 (New): Some templates use rand(-2147483648, 2147483647) for ran...https://forge.ispras.ru/issues/99782019-12-10T21:39:00ZAlexander Kamkinaskamkin@gmail.com
<p>It looks strange and needs to be fixed.</p> Aspectrace - Task #9846 (Resolved): Source code formatting and improvementhttps://forge.ispras.ru/issues/98462019-10-04T07:46:54ZAlexander Kamkinaskamkin@gmail.com
<ol>
<li>Transform CP866, Windows 1251, and KOI8-R to UTF8 (done).</li>
<li>Translate Russian comments into English.</li>
<li>Apply Google's Java style convention.</li>
<li>Improve the source code (add @Override, final, etc.).</li>
</ol> Verilog Translator - Bug #8797 (New): Error when using multiple includeshttps://forge.ispras.ru/issues/87972018-04-03T12:17:52ZAlexander Kamkinaskamkin@gmail.com
<p>Something strange happens when including several files in a raw.</p>